Design Store

max10_neek_tft_controller   

CategoryDesign Example
Namemax10_neek_tft_controller
DescriptionThe TFT Graphical Controller Example Design demonstrates Intel Max10 FPGAs in a graphics system. The example design runs on the MAX 10 NEEK board.
Operating SystemNone
IP Core
IP CoreHeading
Clocked Video Output II (4K Ready)Video and Image Processing
Video Input BridgeComponent Library
Mixer II (4K Ready)Video and Image Processing
Scaler IIVideo and Image Processing
Scaler Algorithmic CoreComponent Library
Frame ReaderVideo and Image Processing
Avalon ALTPLLPLL
Avalon-MM Clock Crossing BridgeMemory Mapped
IRQ MapperInterrupt
IRQ Clock CrosserInterrupt
JTAG UARTSerial
PIO (Parallel I/O)Peripherals
DDR3 SDRAM Controller with UniPHYMemory Interfaces with UniPHY
Altera DDR3 Nextgen Memory ControllerMemory Controllers
Altera Nextgen Memory Controller MM-ST AdapterMemory Controller Components
Altera DDR3 Nextgen Memory Controller CoreMemory Controller Components
Altera DDR3 AFI MultiplexerMemory AFI Multiplexers
DDR3 SDRAM External Memory PHYMemory PHYs
DDR3 SDRAM External Memory PLL/DLL/OCT blockMemory PHYs
DDR3 SDRAM Qsys SequencerMemory Sequencers
Avalon-MM Master AgentMemory-Mapped
Avalon-MM Master TranslatorMemory-Mapped
Avalon-MM Slave AgentMemory-Mapped
Avalon-ST Single Clock FIFOOn Chip Memory
Avalon-MM Slave TranslatorMemory-Mapped
MM InterconnectMerlin Components
Avalon-ST Pipeline StageStreaming
Avalon-ST AdapterStreaming
Avalon-ST Error AdapterStreaming
Memory-Mapped DemultiplexerMemory-Mapped
Memory-Mapped MultiplexerMemory-Mapped
Avalon-ST Handshake Clock CrosserStreaming
Memory-Mapped Width AdapterMemory-Mapped
Memory-Mapped Traffic LimiterMemory-Mapped
Memory-Mapped RouterMemory-Mapped
Nios II Gen2 ProcessorNios
On-Chip Memory (RAM or ROM)On Chip Memory
Reset ControllerClocks; PLLs and Resets
System ID PeripheralDebug and Performance
Interval TimerPeripherals
Version1.0
FamilyMAX 10
Device10M50DA
Documentation
DocumentDescription
NEEK10 TFT Graphical Controller Design ExampleThe TFT Graphical Controller Example Design demonstrates Intel Max10 FPGAs in a graphics system. The example design runs on the MAX 10 NEEK board
Development KitMAX 10 NEEK
Installation Package Download

Note: After downloading the design example, you must prepare the design template. The file you downloaded is of the form of a <project>.par file which contains a compressed version of your design files (similar to a .qar file) and metadata describing the project. The combination of this information is what constitutes a <project>.par file. In releases 16.0 or newer, you can simply double click on the <project>.par file and Quartus will launch that project.

The second means to bring up the project template is through the New Project Wizard (File -> New Project Wizard). After entering the project name and folder on the first panel, the second panel will ask you to specify an empty project or project template. Select project template. You will see a list of Design Templates projects that you have loaded prior as well as various "Baseline Pinout Designs" that contain the pinout and settings for a variety of development kits. If you don't see your design template in the list, click on the link that states install the Design Templates circled below:


Browse to the <project>.par file you downloaded, click next, followed by Finish, and your design template will be installed and displayed in the Project Navigator pane in Quartus.

Note: When a design is stored in the Design Store as a design template, it has been previously regression tested against the stated version of Quartus software. The regression ensures the design template passes analysis/synthesis/fitting/assembly steps in the Quartus design flow.

At the command-line, type the following command:

quartus_sh --platform_install –package <project directory>/max10_neek_tft_controller.par

Once the process completes, then type:

quartus_sh --platform –name max10_neek_tft_controller

Total Downloads11 (From 26 Jan 2017 to 27 Apr 2017)
Quartus II Version Download Quartus II v16.0
VendorAltera


Last updated on Jan. 26, 2017, 11:25 a.m.