Design Store

Nios II Simple Socket Server Ethernet Example  

CategoryDesign Example
NameNios II Simple Socket Server Ethernet Example
DescriptionThis design example demonstrates communication with a telnet client on a development host PC. The telnet client offers a convenient way of issuing
commands over a TCP/IP socket to the Ethernet-connected NicheStack TCP/IP Stackrunning on the Altera development board with a simple TCP/IP socket server example. The socket server example receives commands sent over a TCP/IP connection and turns LEDs on and off according to the commands. Note that this design uses DDR3 memory and the pinout on the devkit changes based on the revision of your kit. See the MAX 10 dev kit baseline pinout design for a TCL script with the pinout changes between the different revisions of the development kits.
Operating SystemNone
IP Core
IP CoreHeading
ALTCLKCTRLClocks; PLLs and Resets
Altera GPIO LiteO
Avalon ALTPLLPLL
Avalon-ST AdapterStreaming
Avalon-ST Timing AdapterStreaming
Nios II Gen2 ProcessorNios
On-Chip Memory (RAM or ROM)On Chip Memory
Altera Dual BootConfiguration
Triple-Speed EthernetEthernet
Altera Generic QUAD SPI controllerFlash
Altera ASMI ParallelConfiguration and Programming
Altera EPCQ Serial Flash controller coreOther
Altera SOFT ASMIBLOCKConfiguration and Programming
IRQ MapperInterrupt
IRQ Clock CrosserInterrupt
JTAG UARTSerial
PIO (Parallel I/O)Peripherals
DDR3 SDRAM Controller with UniPHYMemory Interfaces with UniPHY
Altera DDR3 Nextgen Memory ControllerMemory Controllers
Altera Nextgen Memory Controller MM-ST AdapterMemory Controller Components
Altera DDR3 Nextgen Memory Controller CoreMemory Controller Components
Altera DDR3 AFI MultiplexerMemory AFI Multiplexers
DDR3 SDRAM External Memory PHYMemory PHYs
DDR3 SDRAM External Memory PLL/DLL/OCT blockMemory PHYs
DDR3 SDRAM Qsys SequencerMemory Sequencers
Avalon-MM Master AgentMemory-Mapped
Avalon-MM Master TranslatorMemory-Mapped
Avalon-MM Slave AgentMemory-Mapped
Avalon-ST Single Clock FIFOOn Chip Memory
Avalon-MM Slave TranslatorMemory-Mapped
MM InterconnectMerlin Components
Avalon-ST Error AdapterStreaming
Memory-Mapped DemultiplexerMemory-Mapped
Memory-Mapped MultiplexerMemory-Mapped
Memory-Mapped Traffic LimiterMemory-Mapped
Avalon-ST Handshake Clock CrosserStreaming
Memory-Mapped Burst AdapterMemory-Mapped
Memory-Mapped RouterMemory-Mapped
Reset ControllerClocks; PLLs and Resets
Scatter-Gather DMA ControllerDMA
Interval TimerPeripherals
System ID PeripheralDebug and Performance
Version1.0
FamilyMAX 10
Device10M50DA
Documentation
DocumentDescription
Nios II Simple Socket Server Ethernet Guide-
Using the NicheStack TCP/IP Stack - Nios II Tutorial-
Development KitMAX 10 FPGA Development Kit
Installation Package Download

Note: After downloading the design example, you must prepare the design template. The file you downloaded is of the form of a <project>.par file which contains a compressed version of your design files (similar to a .qar file) and metadata describing the project. The combination of this information is what constitutes a <project>.par file. In releases 16.0 or newer, you can simply double click on the <project>.par file and Quartus will launch that project.

The second means to bring up the project template is through the New Project Wizard (File -> New Project Wizard). After entering the project name and folder on the first panel, the second panel will ask you to specify an empty project or project template. Select project template. You will see a list of Design Templates projects that you have loaded prior as well as various "Baseline Pinout Designs" that contain the pinout and settings for a variety of development kits. If you don't see your design template in the list, click on the link that states install the Design Templates circled below:


Browse to the <project>.par file you downloaded, click next, followed by Finish, and your design template will be installed and displayed in the Project Navigator pane in Quartus.

Note: When a design is stored in the Design Store as a design template, it has been previously regression tested against the stated version of Quartus software. The regression ensures the design template passes analysis/synthesis/fitting/assembly steps in the Quartus design flow.

At the command-line, type the following command:

quartus_sh --platform_install –package <project directory>/devkit_simple_socket_server.par

Once the process completes, then type:

quartus_sh --platform –name devkit_simple_socket_server

Total Downloads113 (From 14 Jun 2016 to 19 Apr 2017)
Quartus II Version Download Quartus II v16.0
VendorAltera


Last updated on June 14, 2016, 2:25 p.m.