Design Store

Nios II Full Featured Reference Design - BeMicro  

CategoryDesign Example
NameNios II Full Featured Reference Design - BeMicro
DescriptionThis is a comprehensive design example which demonstrates how to use the following interfaces on the BeMicro Max 10 FPGA Evaluation kit:
(i) Accelerometer
(ii) Temperature Sensor
(iii) DAC
(iv) ADC
(v) Serial Flash
Operating SystemBareMetal
IP Core
IP CoreHeading
Avalon ALTPLLPLL
PIO (Parallel I/O)Peripherals
Nios II Gen2 ProcessorNios
Nios II Gen2 Processor UnitNios
On-Chip Memory (RAM or ROM)On Chip Memory
IRQ MapperInterrupt
JTAG UARTSerial
MM InterconnectMerlin Components
Avalon-MM Slave AgentMemory-Mapped
Avalon-ST Single Clock FIFOOn Chip Memory
Avalon-MM Slave TranslatorMemory-Mapped
Avalon-ST AdapterStreaming
Avalon-ST Error AdapterStreaming
Memory-Mapped DemultiplexerMemory-Mapped
Memory-Mapped MultiplexerMemory-Mapped
Avalon-MM Master AgentMemory-Mapped
Avalon-MM Master TranslatorMemory-Mapped
Avalon-ST Handshake Clock CrosserStreaming
Memory-Mapped RouterMemory-Mapped
Memory-Mapped Burst AdapterMemory-Mapped
Memory-Mapped Width AdapterMemory-Mapped
Memory-Mapped Traffic LimiterMemory-Mapped
Altera Modular ADC corePeripherals
Altera Modular ADC Control corePeripherals
Altera Modular ADC Sample Storage corePeripherals
Altera Modular ADC Sequencer corePeripherals
Reset ControllerClocks; PLLs and Resets
SDRAM ControllerSDRAM
SPI (3 Wire Serial)Serial
altera_jtag_avalon_masterSystem
Avalon-ST Bytes to Packets ConverterStreaming
Avalon-ST Channel AdapterStreaming
Avalon-ST JTAG InterfaceSerial
Avalon-ST Packets to Bytes ConverterStreaming
Avalon-ST Timing AdapterStreaming
Avalon Packets to Transaction ConverterStreaming
System ID PeripheralDebug and Performance
Interval TimerPeripherals
Altera On-Chip FlashOn Chip Memory
Version1.02
FamilyMAX 10
Device10M08DA
Documentation
DocumentDescription
Full Featured Reference Design User Guide-
Development KitBeMicro MAX 10 FPGA Evaluation Kit
Installation Package Download

Note: After downloading the design example, you must prepare the design template. The file you downloaded is of the form of a <project>.par file which contains a compressed version of your design files (similar to a .qar file) and metadata describing the project. The combination of this information is what constitutes a <project>.par file. In releases 16.0 or newer, you can simply double click on the <project>.par file and Quartus will launch that project.

The second means to bring up the project template is through the New Project Wizard (File -> New Project Wizard). After entering the project name and folder on the first panel, the second panel will ask you to specify an empty project or project template. Select project template. You will see a list of Design Templates projects that you have loaded prior as well as various "Baseline Pinout Designs" that contain the pinout and settings for a variety of development kits. If you don't see your design template in the list, click on the link that states install the Design Templates circled below:


Browse to the <project>.par file you downloaded, click next, followed by Finish, and your design template will be installed and displayed in the Project Navigator pane in Quartus.

Note: When a design is stored in the Design Store as a design template, it has been previously regression tested against the stated version of Quartus software. The regression ensures the design template passes analysis/synthesis/fitting/assembly steps in the Quartus design flow.

At the command-line, type the following command:

quartus_sh --platform_install –package <project directory>/BeMicro_full_reference.par

Once the process completes, then type:

quartus_sh --platform –name BeMicro_full_reference

Total Downloads77 (From 27 Sep 2016 to 24 Mar 2017)
Quartus II Version Download Quartus II v16.0
VendorArrow


Last updated on Sept. 27, 2016, 12:05 p.m.