Design Store

MIPI CSI2 RX/TX with passive D-PHY  

CategoryDesign Example
NameMIPI CSI2 RX/TX with passive D-PHY
DescriptionIf interested in purchasing or evaluating this IP core, please send an email request to ip@foresys.com to request a license for either the MIPI CSI-2 TX Core or MIPI CSI-2 RX Core.

This reference design provides an example of video processing of a camera sensor via the MIPI CSI-2 RX and TX interfaces using an external passive D-PHY resistor network.

RX path includes:
- External Camera Sensor [Leopard Imaging LI-CAM-OV10640-MIPI OVT10640 (4D+C)] transmits video stream across MIPI CSI-2 RX interface.
- The Foresys MIPI-RX Core performs the MIPI CSI-2 layer processing and forwards the video stream as Avalon Streaming Video.
- Altera VIP components (process video data)
- The RX Video stream is forwarded to an external monitor via the HDMI connector on the board.

TX path includes:
- The Foresys MIPI-TX Core encodes the Avalon Streaming video stream as MIPI CSI-2 layer formatting and forwards the stream out the MIPI CSI-2 TX connector.
- An external Leopard Imaging [LI-USB30-MIPI-TESTER (CSI2 to USB3 Bridge)] converts the stream to USB3 format.
- The USB3 cable forwards the stream to an external host computer.
Operating SystemBareMetal
IP Core
IP CoreHeading
Altera Soft LVDSO
FIFOOn Chip Memory
Avalon ALTPLLPLL
Altera GPIO LiteO
Test Pattern Generator II (4K Ready)Video and Image Processing
Frame Buffer II (4K Ready)Video and Image Processing
Video Input BridgeComponent Library
Clocked Video OutputVideo and Image Processing
PIO (Parallel I/O)Peripherals
IRQ MapperInterrupt
JTAG UARTSerial
altera_jtag_avalon_masterSystem
Avalon-ST Bytes to Packets ConverterStreaming
Avalon-ST Channel AdapterStreaming
Avalon-ST Single Clock FIFOOn Chip Memory
Avalon-ST JTAG InterfaceSerial
Avalon-ST Packets to Bytes ConverterStreaming
Reset ControllerClocks; PLLs and Resets
Avalon-ST Timing AdapterStreaming
Avalon Packets to Transaction ConverterStreaming
LPDDR2 SDRAM Controller with UniPHYMemory Interfaces with UniPHY
Altera LPDDR2 Nextgen Memory ControllerMemory Controllers
Altera Nextgen Memory Controller MM-ST AdapterMemory Controller Components
Altera LPDDR2 Nextgen Memory Controller CoreMemory Controller Components
Altera LPDDR2 AFI MultiplexerMemory AFI Multiplexers
LPDDR2 SDRAM External Memory PHYMemory PHYs
LPDDR2 SDRAM External Memory PLL/DLL/OCT blockMemory PHYs
LPDDR2 SDRAM Qsys SequencerMemory Sequencers
Avalon-MM Master AgentMemory-Mapped
Avalon-MM Master TranslatorMemory-Mapped
Avalon-MM Slave AgentMemory-Mapped
Avalon-MM Slave TranslatorMemory-Mapped
Avalon-MM Pipeline BridgeMemory Mapped
MM InterconnectMerlin Components
Avalon-ST AdapterStreaming
Avalon-ST Error AdapterStreaming
Memory-Mapped DemultiplexerMemory-Mapped
Memory-Mapped MultiplexerMemory-Mapped
Memory-Mapped RouterMemory-Mapped
Memory-Mapped Burst AdapterMemory-Mapped
Nios II Gen2 ProcessorNios
Nios II Gen2 Processor UnitNios
On-Chip Memory (RAM or ROM)On Chip Memory
Version2.2
FamilyMAX 10
Device10M50DA
Development KitMAX 10 FPGA 10M50 Evaluation Kit
Installation Package Download

Note: After downloading the design example, you must prepare the design template. The file you downloaded is of the form of a <project>.par file which contains a compressed version of your design files (similar to a .qar file) and metadata describing the project. The combination of this information is what constitutes a <project>.par file. In releases 16.0 or newer, you can simply double click on the <project>.par file and Quartus will launch that project.

The second means to bring up the project template is through the New Project Wizard (File -> New Project Wizard). After entering the project name and folder on the first panel, the second panel will ask you to specify an empty project or project template. Select project template. You will see a list of Design Templates projects that you have loaded prior as well as various "Baseline Pinout Designs" that contain the pinout and settings for a variety of development kits. If you don't see your design template in the list, click on the link that states install the Design Templates circled below:


Browse to the <project>.par file you downloaded, click next, followed by Finish, and your design template will be installed and displayed in the Project Navigator pane in Quartus.

Note: When a design is stored in the Design Store as a design template, it has been previously regression tested against the stated version of Quartus software. The regression ensures the design template passes analysis/synthesis/fitting/assembly steps in the Quartus design flow.

At the command-line, type the following command:

quartus_sh --platform_install –package <project directory>/mipi_to_hdmi_v0202.par

Once the process completes, then type:

quartus_sh --platform –name mipi_to_hdmi_v0202

Total Downloads127 (From 04 Oct 2016 to 24 Mar 2017)
Quartus II Version Download Quartus II v16.0
VendorForesys


Last updated on Nov. 2, 2016, 8:06 a.m.