|Name||MAX10 10M50 Development Kit GHRD with Nios II/DDR3/QSPI Flash/Ethernet/mSGDMA/UART/ADC with Linux|
|Description||This is the new and updated Golden Hardware Reference Design (GHRD) for Altera MAX 10 FPGA Development Kit with addition of modular ADC component.|
The GHRD is an important part of the Golden System Reference Design (GSRD) and consists of the following components:
- Nios II Gen2 Processor with memory management unit (MMU) enabled
- DDR3 SDRAM controller
- Quad SPI controller
- RGMII Gigabit Ethernet
- Modular SGDMA
- Modular ADC
- PIO access to button and LED
- System Clock
- On-chip memory
- System ID
- JTAG for debugging purposes
User can choose to boot up MAX10 10M50 Rev C development kit with Nios II Linux using this GHRD design. Linux setup guidelines can be found in the Documentation link.
This design by default has Rev C pinout in the Pin Planner. If you would like to change the pinout to Rev B, go to Tools -> Tcl Scripts and select RevC_to_RevB.tcl and hit Run.
If you want to go back to Rev C, you can execute RevB_to_RevC.tcl pinout.
To find out the Revision of your board, look at the back of the board towards the bottom center. You can also refer to the image on design store.
|Development Kit||MAX 10 FPGA Development Kit|
|Quartus II Version||Download Quartus II v16.0|
Last updated on Feb. 2, 2017, 8:10 a.m.