Design Store

DDR3 with Board Test System Console  

CategoryDesign Example
NameDDR3 with Board Test System Console
DescriptionThe MAX 10 FPGA development kit has one 64-Mx16 1Gb DDR3 SDRAM and one 128-Mx8 1Gb DDR3 SDRAM. The MAX 10 FPGA provides full-speed support to a DDR3 300-MHz interface with error correction code (ECC) feature. This design example is used to check out a x24 DDR3 300MHz interface, please download the installer of MAX 10 development kit and use BTS GUI to try it out for a straightforward experience. Note that this design uses DDR3 memory and the pinout on the devkit changes based on the revision of your kit. See the MAX 10 dev kit baseline pinout design for a TCL script with the pinout changes between the different revisions of the development kits.
Operating SystemNone
IP Core
IP CoreHeading
IRQ MapperInterrupt
IRQ Clock CrosserInterrupt
altera_jtag_avalon_masterSystem
Avalon-ST Bytes to Packets ConverterStreaming
Avalon-ST Channel AdapterStreaming
Avalon-ST Single Clock FIFOOn Chip Memory
Avalon-ST JTAG InterfaceSerial
Avalon-ST Packets to Bytes ConverterStreaming
Reset ControllerClocks; PLLs and Resets
Avalon-ST Timing AdapterStreaming
Avalon Packets to Transaction ConverterStreaming
DDR3 SDRAM Controller with UniPHYMemory Interfaces with UniPHY
Altera DDR3 Nextgen Memory ControllerMemory Controllers
Altera Nextgen Memory Controller MM-ST AdapterMemory Controller Components
Altera DDR3 Nextgen Memory Controller CoreMemory Controller Components
Altera DDR3 AFI MultiplexerMemory AFI Multiplexers
DDR3 SDRAM External Memory PHYMemory PHYs
DDR3 SDRAM External Memory PLL/DLL/OCT blockMemory PHYs
DDR3 SDRAM Qsys SequencerMemory Sequencers
Avalon-MM Master AgentMemory-Mapped
Avalon-MM Master TranslatorMemory-Mapped
Avalon-MM Slave AgentMemory-Mapped
Avalon-MM Slave TranslatorMemory-Mapped
MM InterconnectMerlin Components
Avalon-ST AdapterStreaming
Avalon-ST Error AdapterStreaming
Memory-Mapped DemultiplexerMemory-Mapped
Memory-Mapped MultiplexerMemory-Mapped
Avalon-ST Handshake Clock CrosserStreaming
Memory-Mapped RouterMemory-Mapped
Memory-Mapped Burst AdapterMemory-Mapped
Memory-Mapped Width AdapterMemory-Mapped
Memory-Mapped Traffic LimiterMemory-Mapped
Modular SGDMA DispatchermSGDMA Sub-core
Read MastermSGDMA Sub-core
Write MastermSGDMA Sub-core
Avalon-MM Pipeline BridgeMemory Mapped
Avalon-ST Pipeline StageStreaming
Avalon-ST Dual Clock FIFOOn Chip Memory
Interval TimerPeripherals
Version1.0
FamilyMAX 10
Device10M50DA
Documentation
DocumentDescription
DDR3_Using_MAX_10_FPGA_Development_KitThis is a simple design spec for DDR3 design example for MAX 10 FPGA development kit
Development KitMAX 10 FPGA Development Kit
Installation Package Download

Note: After downloading the design example, you must prepare the design template. The file you downloaded is of the form of a <project>.par file which contains a compressed version of your design files (similar to a .qar file) and metadata describing the project. The combination of this information is what constitutes a <project>.par file. In releases 16.0 or newer, you can simply double click on the <project>.par file and Quartus will launch that project.

The second means to bring up the project template is through the New Project Wizard (File -> New Project Wizard). After entering the project name and folder on the first panel, the second panel will ask you to specify an empty project or project template. Select project template. You will see a list of Design Templates projects that you have loaded prior as well as various "Baseline Pinout Designs" that contain the pinout and settings for a variety of development kits. If you don't see your design template in the list, click on the link that states install the Design Templates circled below:


Browse to the <project>.par file you downloaded, click next, followed by Finish, and your design template will be installed and displayed in the Project Navigator pane in Quartus.

Note: When a design is stored in the Design Store as a design template, it has been previously regression tested against the stated version of Quartus software. The regression ensures the design template passes analysis/synthesis/fitting/assembly steps in the Quartus design flow.

At the command-line, type the following command:

quartus_sh --platform_install –package <project directory>/ddr3.par

Once the process completes, then type:

quartus_sh --platform –name ddr3

Total Downloads58 (From 18 Jul 2016 to 27 Apr 2017)
Quartus II Version Download Quartus II v16.0
VendorAltera


Last updated on July 18, 2016, 11:52 a.m.