Design Store

Using MAX 10 and Nios II to replace Freescale MC9S08 Microcontrollers  

CategoryDesign Example
NameUsing MAX 10 and Nios II to replace Freescale MC9S08 Microcontrollers
DescriptionThe design example is intended as a Freescale MC9S08 Qsys HDL (Verilog) Design Template. The AMC1 is intended to illustrate how an Altera MAX 10 device with Nios II may be used in low cost, automotive and industrial embedded environments.While there is no ISA or binary compatibility in this example when replacing the MC9S08, most of the hardware functionality is available with a Nios II solution.
Operating SystemBareMetal
IP Core
IP CoreHeading
Avalon ALTPLLPLL
IRQ MapperInterrupt
IRQ Clock CrosserInterrupt
MM InterconnectMerlin Components
Avalon-MM Slave AgentMemory-Mapped
Avalon-ST Single Clock FIFOOn Chip Memory
Avalon-MM Slave TranslatorMemory-Mapped
Avalon-ST AdapterStreaming
Avalon-ST Error AdapterStreaming
Memory-Mapped DemultiplexerMemory-Mapped
Memory-Mapped MultiplexerMemory-Mapped
Avalon-ST Handshake Clock CrosserStreaming
Error Response SlaveMemory-Mapped
AXI Slave AgentMemory-Mapped
Avalon-MM Master AgentMemory-Mapped
Avalon-MM Master TranslatorMemory-Mapped
Memory-Mapped RouterMemory-Mapped
Altera Modular ADC corePeripherals
Altera Modular ADC Control corePeripherals
Altera Modular ADC Sample Storage corePeripherals
Altera Modular ADC Sequencer corePeripherals
Nios II Gen2 ProcessorNios
Nios II Gen2 Processor UnitNios
Altera On-Chip FlashOn Chip Memory
On-Chip Memory (RAM or ROM)On Chip Memory
FIFOOn Chip Memory
PIO (Parallel I/O)Peripherals
Reset ControllerClocks; PLLs and Resets
SPI (3 Wire Serial)Serial
Interval TimerPeripherals
UART (RS-232 Serial Port)Serial
Version1.0
FamilyMAX 10
Device10M08SC
Documentation
DocumentDescription
User Guide - replacement of Freescale uC with MAX 10 and Nios-
Development KitNon Kit Specific MAX 10 Design Examples
Installation Package Download

Note: After downloading the design example, you must prepare the design template. The file you downloaded is of the form of a <project>.par file which contains a compressed version of your design files (similar to a .qar file) and metadata describing the project. The combination of this information is what constitutes a <project>.par file. In releases 16.0 or newer, you can simply double click on the <project>.par file and Quartus will launch that project.

The second means to bring up the project template is through the New Project Wizard (File -> New Project Wizard). After entering the project name and folder on the first panel, the second panel will ask you to specify an empty project or project template. Select project template. You will see a list of Design Templates projects that you have loaded prior as well as various "Baseline Pinout Designs" that contain the pinout and settings for a variety of development kits. If you don't see your design template in the list, click on the link that states install the Design Templates circled below:


Browse to the <project>.par file you downloaded, click next, followed by Finish, and your design template will be installed and displayed in the Project Navigator pane in Quartus.

Note: When a design is stored in the Design Store as a design template, it has been previously regression tested against the stated version of Quartus software. The regression ensures the design template passes analysis/synthesis/fitting/assembly steps in the Quartus design flow.

At the command-line, type the following command:

quartus_sh --platform_install –package <project directory>/orchid_HC8S08.par

Once the process completes, then type:

quartus_sh --platform –name orchid_HC8S08

Total Downloads15 (From 25 May 2016 to 24 Mar 2017)
Quartus II Version Download Quartus II v16.0
Quartus II EditionStandard
VendorAltera


Last updated on May 25, 2016, 5:57 p.m.