|Name||Power Management Controller|
|Description||The power management controller reference design allows you to allocate some applications in sleep mode during runtime. This reference design includes a simple finite state machine (FSM) to manage low-power state mode by powering down the I/O buffer and GCLK gating during sleep mode. This enables you to turn off portions of the design, thus reducing dynamic power consumption. You can re-enable your application with a fast wake-up time of less than 1 ms. You can modify the reference design based on your application.|
|Development Kit||MAX 10 FPGA Development Kit|
Note: After downloading the design example, you must prepare the design template. The file you downloaded is of the form of a <project>.par file which contains a compressed version of your design files (similar to a .qar file) and metadata describing the project. The combination of this information is what constitutes a <project>.par file. In releases 16.0 or newer, you can simply double click on the <project>.par file and Quartus will launch that project.
Browse to the <project>.par file you downloaded, click next, followed by Finish, and your design template will be installed and displayed in the Project Navigator pane in Quartus.
Note: When a design is stored in the Design Store as a design template, it has been previously regression tested against the stated version of Quartus software. The regression ensures the design template passes analysis/synthesis/fitting/assembly steps in the Quartus design flow.
At the command-line, type the following command:
Once the process completes, then type:
|Total Downloads||57 (From 02 Jun 2016 to 04 Oct 2017)|
|Quartus II Version||Download Quartus II v16.0|
|Quartus II Edition||Standard|
Last updated on June 2, 2016, 11:35 a.m.