Design Store

Nios II + Qsys "Hello World" Lab  

CategoryTutorial
NameNios II + Qsys "Hello World" Lab
DescriptionThis step by step lab shows a user how to build a Nios II Qsys based system that includes GPIO, UART and on-chip memory. This lab requires the MAX 10 Development Kit from Altera. The appendix B in the lab manual describes how to combine the SW image with the HW .sof file.
Operating SystemBareMetal
IP Core
IP CoreHeading
IRQ MapperInterrupt
PIO (Parallel I/O)Peripherals
MM InterconnectMerlin Components
Avalon-ST AdapterStreaming
Avalon-ST Error AdapterStreaming
Memory-Mapped DemultiplexerMemory-Mapped
Memory-Mapped MultiplexerMemory-Mapped
Avalon-MM Slave AgentMemory-Mapped
Avalon-ST Single Clock FIFOOn Chip Memory
Avalon-MM Slave TranslatorMemory-Mapped
Avalon-MM Master AgentMemory-Mapped
Avalon-MM Master TranslatorMemory-Mapped
Memory-Mapped RouterMemory-Mapped
Nios II Gen2 ProcessorNios
Nios II Gen2 Processor UnitNios
On-Chip Memory (RAM or ROM)On Chip Memory
Reset ControllerClocks; PLLs and Resets
JTAG UARTSerial
Version1.0
FamilyMAX 10
Device10M50DA
Documentation
DocumentDescription
Hello World Lab Main Manual for MAX 10Main Manual for the Hello World Lab on the MAX 10 FPGA Development Kit
Nios II Hardware Development Online Training ClassFree Nios II Hardware Online Training
Nios II Software Development Online Training ClassFree Nios II Software Online Training
Appendix A: MAX 10 Hardware PinoutAppendix A: Hardware Pinout for MAX 10 FPGA Development Kit
Appendix B: Using Schematic CaptureAppendix B: Using Schematic Capture in Place of Writing Verilog for the Top Level Module
Appendix C: Merging Nios Executable into the FPGA Configuration FileAppendix C: Merging Nios Executable into the FPGA Configuration File (Hardware Image) for the MAX 10 FPGA Development Kit
Appendix D: Using Interrupt Service RoutinesAppendix D: Using Interrupt Service Routines (ISR) in a Nios Based System
Development KitMAX 10 FPGA Development Kit
Installation Package Download

Note: After downloading the design example, you must prepare the design template. The file you downloaded is of the form of a <project>.par file which contains a compressed version of your design files (similar to a .qar file) and metadata describing the project. The combination of this information is what constitutes a <project>.par file. In releases 16.0 or newer, you can simply double click on the <project>.par file and Quartus will launch that project.

The second means to bring up the project template is through the New Project Wizard (File -> New Project Wizard). After entering the project name and folder on the first panel, the second panel will ask you to specify an empty project or project template. Select project template. You will see a list of Design Templates projects that you have loaded prior as well as various "Baseline Pinout Designs" that contain the pinout and settings for a variety of development kits. If you don't see your design template in the list, click on the link that states install the Design Templates circled below:


Browse to the <project>.par file you downloaded, click next, followed by Finish, and your design template will be installed and displayed in the Project Navigator pane in Quartus.

Note: When a design is stored in the Design Store as a design template, it has been previously regression tested against the stated version of Quartus software. The regression ensures the design template passes analysis/synthesis/fitting/assembly steps in the Quartus design flow.

At the command-line, type the following command:

quartus_sh --platform_install –package <project directory>/hello_world_lab.par

Once the process completes, then type:

quartus_sh --platform –name hello_world_lab

Total Downloads114 (From 25 May 2016 to 21 Jun 2017)
Quartus II Version Download Quartus II v16.0
Quartus II EditionStandard
VendorAltera


Last updated on May 25, 2016, 10:40 a.m.