Design Store

Nios II + Qsys "Hello World" Lab - MAX10 DE10 Lite  

NameNios II + Qsys "Hello World" Lab - MAX10 DE10 Lite
DescriptionThis step by step lab shows a user how to build a Nios II Qsys based system that includes GPIO, UART and on-chip memory. This lab requires the MAX 10 DE10-Lite Development Kit from Terasic. The appendix B in the lab manual describes how to combine the SW image with the HW .sof file.
Operating SystemNone
IP Core
IP CoreHeading
IRQ MapperInterrupt
PIO (Parallel I/O)Peripherals
MM InterconnectMerlin Components
Avalon-ST AdapterStreaming
Avalon-ST Error AdapterStreaming
Memory-Mapped DemultiplexerMemory-Mapped
Memory-Mapped MultiplexerMemory-Mapped
Avalon-MM Slave AgentMemory-Mapped
Avalon-ST Single Clock FIFOOn Chip Memory
Avalon-MM Slave TranslatorMemory-Mapped
Avalon-MM Master AgentMemory-Mapped
Avalon-MM Master TranslatorMemory-Mapped
Memory-Mapped RouterMemory-Mapped
Nios II Gen2 ProcessorNios
Nios II Gen2 Processor UnitNios
On-Chip Memory (RAM or ROM)On Chip Memory
Reset ControllerClocks; PLLs and Resets
FamilyMAX 10
Hello World Lab Manual for MAX 10 DE10-LiteMain Manual for the Hello World Lab on the DE10-Lite Development Kit
Development KitMAX 10 DE10 - Lite
Quartus II VersionDownload Quartus II v16.0
Quartus II EditionStandard

Last updated on June 13, 2017, 6:22 p.m.