Design Store

Nios II Qsys Example with Capsense, Humidty and Temperature Sensors  

CategoryDesign Example
NameNios II Qsys Example with Capsense, Humidty and Temperature Sensors
DescriptionThis design example creates an embedded system implemented in programmable logic. A processor-based hardware system is built and software is run on it.
Note that this design is extracted from Arrow's DECA workshop series of labs.This is the final solution only. If you would like to work through the lab and learn more about it, visit: http://www.arrow.com/campaigns-na/altera/deca/.
Operating SystemNone
IP Core
IP CoreHeading
Avalon ALTPLLPLL
PIO (Parallel I/O)Peripherals
IRQ MapperInterrupt
IRQ Clock CrosserInterrupt
JTAG UARTSerial
MM InterconnectMerlin Components
Avalon-MM Slave AgentMemory-Mapped
Avalon-ST Single Clock FIFOOn Chip Memory
Avalon-MM Slave TranslatorMemory-Mapped
Avalon-ST AdapterStreaming
Avalon-ST Error AdapterStreaming
Memory-Mapped DemultiplexerMemory-Mapped
Memory-Mapped MultiplexerMemory-Mapped
Avalon-ST Handshake Clock CrosserStreaming
Avalon-MM Master AgentMemory-Mapped
Avalon-MM Master TranslatorMemory-Mapped
Memory-Mapped RouterMemory-Mapped
Memory-Mapped Traffic LimiterMemory-Mapped
Altera Modular ADC corePeripherals
Altera Modular ADC Control corePeripherals
Altera Modular ADC Sample Storage corePeripherals
Altera Modular ADC Sequencer corePeripherals
Nios II Gen2 ProcessorNios
Nios II Gen2 Processor UnitNios
On-Chip Memory (RAM or ROM)On Chip Memory
Reset ControllerClocks; PLLs and Resets
Avalon-MM Clock Crossing BridgeMemory Mapped
System ID PeripheralDebug and Performance
Interval TimerPeripherals
Altera On-Chip FlashOn Chip Memory
Version1.0
FamilyMAX 10
Device10M50DA
Documentation
DocumentDescription
Arrow DECA Product Page-
Qsys Design Lab Manual-
Development KitArrow MAX 10 DECA
Installation Package Download

Note: After downloading the design example, you must prepare the design template. The file you downloaded is of the form of a <project>.par file which contains a compressed version of your design files (similar to a .qar file) and metadata describing the project. The combination of this information is what constitutes a <project>.par file. In releases 16.0 or newer, you can simply double click on the <project>.par file and Quartus will launch that project.

The second means to bring up the project template is through the New Project Wizard (File -> New Project Wizard). After entering the project name and folder on the first panel, the second panel will ask you to specify an empty project or project template. Select project template. You will see a list of Design Templates projects that you have loaded prior as well as various "Baseline Pinout Designs" that contain the pinout and settings for a variety of development kits. If you don't see your design template in the list, click on the link that states install the Design Templates circled below:


Browse to the <project>.par file you downloaded, click next, followed by Finish, and your design template will be installed and displayed in the Project Navigator pane in Quartus.

Note: When a design is stored in the Design Store as a design template, it has been previously regression tested against the stated version of Quartus software. The regression ensures the design template passes analysis/synthesis/fitting/assembly steps in the Quartus design flow.

At the command-line, type the following command:

quartus_sh --platform_install –package <project directory>/3_Embedded_Systems_Lab.par

Once the process completes, then type:

quartus_sh --platform –name 3_Embedded_Systems_Lab

Total Downloads33 (From 03 Jun 2016 to 21 Jun 2017)
Quartus II Version Download Quartus II v16.0
Quartus II EditionStandard
VendorArrow


Image 3


Last updated on June 3, 2016, 10:56 a.m.