Design Store

NEEK 10 test system - running uC/OS  

CategoryDesign Example
NameNEEK 10 test system - running uC/OS
DescriptionThe configurable Nios II system targeted at the MAX 10 NEEK board, the objective is to provide the customer with a design that tests individual peripherals. This integrated platform includes hardware, intellectual property(IP) and embedded software based on uC/OS-II. This design interfaces with each hardware component on the MAX10 NEEK board.
Operating SystemOther
IP Core
IP CoreHeading
Altera Modular ADC corePeripherals
Altera Modular ADC Control corePeripherals
Altera GPIO LiteIO
PIO (Parallel I/O)Peripherals
On-Chip Memory (RAM or ROM)On Chip Memory
Clocked Video Output II (4K Ready)Video and Image Processing
alt_vip_cvo_coreComponent Library
CVO schedulerComponent Library
SwitchVideo and Image Processing
Frame ReaderVideo and Image Processing
Avalon-ST AdapterStreaming
Avalon-ST Timing AdapterStreaming
Altera Generic QUAD SPI controllerFlash
Altera ASMI ParallelConfiguration and Programming
Altera EPCQ Serial Flash controller coreOther
Altera SOFT ASMIBLOCKConfiguration and Programming
IRQ MapperInterrupt
IRQ Clock CrosserInterrupt
DDR3 SDRAM Controller with UniPHYMemory Interfaces with UniPHY
Altera DDR3 Nextgen Memory ControllerMemory Controllers
Altera Nextgen Memory Controller MM-ST AdapterMemory Controller Components
Altera DDR3 Nextgen Memory Controller CoreMemory Controller Components
Altera DDR3 AFI MultiplexerMemory AFI Multiplexers
DDR3 SDRAM External Memory PHYMemory PHYs
DDR3 SDRAM External Memory PLL/DLL/OCT blockMemory PHYs
DDR3 SDRAM Qsys SequencerMemory Sequencers
Avalon-MM Master AgentMemory-Mapped
Avalon-MM Master TranslatorMemory-Mapped
Avalon-MM Slave AgentMemory-Mapped
Avalon-ST Single Clock FIFOOn Chip Memory
Avalon-MM Slave TranslatorMemory-Mapped
Avalon-MM Clock Crossing BridgeMemory Mapped
MM InterconnectMerlin Components
Memory-Mapped Burst AdapterMemory-Mapped
Memory-Mapped Width AdapterMemory-Mapped
Avalon-ST Pipeline StageStreaming
Avalon-ST Error AdapterStreaming
Memory-Mapped DemultiplexerMemory-Mapped
Memory-Mapped MultiplexerMemory-Mapped
Avalon-ST Handshake Clock CrosserStreaming
Memory-Mapped Traffic LimiterMemory-Mapped
Memory-Mapped RouterMemory-Mapped
Nios II Gen2 ProcessorNios
Reset ControllerClocks; PLLs and Resets
Scatter-Gather DMA ControllerDMA
System ID PeripheralDebug and Performance
Interval TimerPeripherals
Triple-Speed EthernetEthernet
FamilyMAX 10
NEEK10_NIOS_Design_ExampleDocument describing the design architecture, what results to expect when running this design on the MAX10 NEEK and how to reconstruct the design.
Development KitMAX 10 NEEK
Installation Package

Note: After downloading the design example, you must prepare the design template. The file you downloaded is of the form of a <project>.par file which contains a compressed version of your design files (similar to a .qar file) and metadata describing the project. The combination of this information is what constitutes a <project>.par file. In releases 16.0 or newer, you can simply double click on the <project>.par file and Quartus will launch that project.

The second means to bring up the project template is through the New Project Wizard (File -> New Project Wizard). After entering the project name and folder on the first panel, the second panel will ask you to specify an empty project or project template. Select project template. You will see a list of Design Templates projects that you have loaded prior as well as various "Baseline Pinout Designs" that contain the pinout and settings for a variety of development kits. If you don't see your design template in the list, click on the link that states install the Design Templates circled below:

Browse to the <project>.par file you downloaded, click next, followed by Finish, and your design template will be installed and displayed in the Project Navigator pane in Quartus.

Note: When a design is stored in the Design Store as a design template, it has been previously regression tested against the stated version of Quartus software. The regression ensures the design template passes analysis/synthesis/fitting/assembly steps in the Quartus design flow.

At the command-line, type the following command:

quartus_sh --platform_install –package <project directory>/neek10_test.par

Once the process completes, then type:

quartus_sh --platform –name neek10_test

Total Downloads8 (From 25 May 2016 to 12 Jul 2017)
Quartus II VersionDownload Quartus II v16.0
Quartus II EditionStandard

Last updated on May 25, 2016, 8:55 a.m.