|Name||NAND Flash Memory Interface (AN 500)|
|Description||Flash memory is a non-volatile form of semiconductor memory that can be electrically programmed and reprogrammed. It stores information in arrays of cells, with each cell storing one bit of information. The cells have a dual gate structure in which a floating gate exists between a control gate and the silicon substrate of a MOSFET. A silicon-dioxide insulator is used to isolate this floating gate. This is the basic storage mechanism of a flash memory device. |
NOR flash and NAND flash are two variations of flash memory devices. A NOR-type flash memory allows random access, whereas NAND-type flash memory is a sequential access device. These two types vary largely in their interface. NOR-type flash memories incorporate dedicated address lines and data lines, whereas NAND-type memories have no dedicated address lines.
Comparison of a NOR-type with a NAND-type yields significant advantages, such as lower cost per bit due to smaller cell area, higher density, better endurance, and lower erasing and programming time for a NAND-type. These advantages make the NAND Flash memory a better choice for use in products, such as: USB flash drives, mp3 players, digital audio recording, data storage in digital Telephone Answering Devices (TAD), digital cameras, and in memory cards like CompactFlash and MemoryStick.
This document details the implementation of a NAND Flash Memory Interface in an Altera MAX 10 FPGA. You can use the design with both SAMSUNG and AMD NAND Flash memories. The AMD Am30LV0064D and Samsung K9F4008W0A flash devices are used in the example.
The AMD NAND Flash device (Am30LV0064D) is a 64-Mbit mass storage device suited for high density applications in which data is sequential and requires fast write capability. The initial page read access time is 7 us with subsequent byte accesses of less than 50 ns.
|Development Kit||Non Kit Specific MAX 10 Design Examples|
|Installation Package|| Download|
Note: After downloading the design example, you must prepare the design template. The file you downloaded is of the form of a <project>.par file which contains a compressed version of your design files (similar to a .qar file) and metadata describing the project. The combination of this information is what constitutes a <project>.par file. In releases 16.0 or newer, you can simply double click on the <project>.par file and Quartus will launch that project.
Browse to the <project>.par file you downloaded, click next, followed by Finish, and your design template will be installed and displayed in the Project Navigator pane in Quartus.
Note: When a design is stored in the Design Store as a design template, it has been previously regression tested against the stated version of Quartus software. The regression ensures the design template passes analysis/synthesis/fitting/assembly steps in the Quartus design flow.
At the command-line, type the following command:
Once the process completes, then type:
|Total Downloads||26 (From 25 May 2016 to 02 May 2017)|
|Quartus II Version||Download Quartus II v16.0|
|Quartus II Edition||Standard|
Last updated on May 25, 2016, 8:30 a.m.