|Name||Max10 Development Kit Baseline Pinout|
|Description||This design contains device pinout only and can be used as a starting point for designing with your MAX10 FPGA Development Kit. You can change the pin names as needed in the Verilog HDL code and the .qsf files (or with the Assignment Editor). Pin locations are locked down on the board.|
Read through the readme file to convert the Rev C baseline to Rev B baseline
|Development Kit||MAX 10 FPGA Development Kit|
|Installation Package|| Download|
Note: After downloading the design example, you must prepare the design template. The file you downloaded is of the form of a <project>.par file which contains a compressed version of your design files (similar to a .qar file) and metadata describing the project. The combination of this information is what constitutes a <project>.par file. In releases 16.0 or newer, you can simply double click on the <project>.par file and Quartus will launch that project.
Browse to the <project>.par file you downloaded, click next, followed by Finish, and your design template will be installed and displayed in the Project Navigator pane in Quartus.
Note: When a design is stored in the Design Store as a design template, it has been previously regression tested against the stated version of Quartus software. The regression ensures the design template passes analysis/synthesis/fitting/assembly steps in the Quartus design flow.
At the command-line, type the following command:
Once the process completes, then type:
|Total Downloads||127 (From 16 Dec 2015 to 21 Jun 2017)|
|Quartus II Version||Download Quartus II v16.0|
|Quartus II Edition||Standard|
Last updated on June 8, 2017, 4:54 p.m.