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MAX10 10M50 Development Kit GHRD with Nios II/DDR3/QSPI Flash/Ethernet/mSGDMA/UART/ADC with Linux  

CategoryDesign Example \ Linux Outside Design Store
NameMAX10 10M50 Development Kit GHRD with Nios II/DDR3/QSPI Flash/Ethernet/mSGDMA/UART/ADC with Linux
DescriptionThis is the new and updated Golden Hardware Reference Design (GHRD) for Altera MAX 10 FPGA Development Kit with addition of modular ADC component.

The GHRD is an important part of the Golden System Reference Design (GSRD) and consists of the following components:
- Nios II Gen2 Processor with memory management unit (MMU) enabled
- DDR3 SDRAM controller
- Quad SPI controller
- RGMII Gigabit Ethernet
- Modular SGDMA
- Modular ADC
- PIO access to button and LED
- System Clock
- On-chip memory
- System ID
- JTAG for debugging purposes

User can choose to boot up MAX10 10M50 Rev C development kit with Nios II Linux using this GHRD design. Linux setup guidelines can be found in the Documentation link.

This design by default has Rev C pinout in the Pin Planner. If you would like to change the pinout to Rev B, go to Tools -> Tcl Scripts and select RevC_to_RevB.tcl and hit Run.
If you want to go back to Rev C, you can execute RevB_to_RevC.tcl pinout.
To find out the Revision of your board, look at the back of the board towards the bottom center. You can also refer to the image on design store.
Operating SystemLinux
IP Core
IP CoreHeading
ALTCLKCTRLClocks; PLLs and Resets
Altera GPIO LiteIO
PIO (Parallel I/O)Peripherals
Nios II Gen2 ProcessorNios
Altera Generic QUAD SPI controllerFlash
Altera ASMI ParallelConfiguration and Programming
Altera EPCQ Serial Flash controller coreOther
Altera SOFT ASMIBLOCKConfiguration and Programming
Altera Interrupt Latency CounterInter-Process Communication
IRQ MapperInterrupt
IRQ Clock CrosserInterrupt
DDR3 SDRAM Controller with UniPHYMemory Interfaces with UniPHY
Altera DDR3 Nextgen Memory ControllerMemory Controllers
Altera Nextgen Memory Controller MM-ST AdapterMemory Controller Components
Altera DDR3 Nextgen Memory Controller CoreMemory Controller Components
Altera DDR3 AFI MultiplexerMemory AFI Multiplexers
DDR3 SDRAM External Memory PHYMemory PHYs
DDR3 SDRAM External Memory PLL/DLL/OCT blockMemory PHYs
DDR3 SDRAM Qsys SequencerMemory Sequencers
Avalon-MM Master AgentMemory-Mapped
Avalon-MM Master TranslatorMemory-Mapped
Avalon-MM Slave AgentMemory-Mapped
Avalon-ST Single Clock FIFOOn Chip Memory
Avalon-MM Slave TranslatorMemory-Mapped
MM InterconnectMerlin Components
Avalon-ST Pipeline StageStreaming
Avalon-ST AdapterStreaming
Avalon-ST Error AdapterStreaming
Memory-Mapped DemultiplexerMemory-Mapped
Memory-Mapped MultiplexerMemory-Mapped
Memory-Mapped Traffic LimiterMemory-Mapped
Avalon-ST Handshake Clock CrosserStreaming
Memory-Mapped Burst AdapterMemory-Mapped
Memory-Mapped Width AdapterMemory-Mapped
Memory-Mapped RouterMemory-Mapped
Altera Modular ADC corePeripherals
Altera Modular ADC Control corePeripherals
Altera Modular ADC Sample Storage corePeripherals
Altera Modular ADC Sequencer corePeripherals
Avalon-ST Timing AdapterStreaming
Triple-Speed EthernetEthernet
Modular Scatter-Gather DMADMA
Modular SGDMA DispatchermSGDMA Sub-core
Write MastermSGDMA Sub-core
Read MastermSGDMA Sub-core
Reset ControllerClocks; PLLs and Resets
Interval TimerPeripherals
System ID PeripheralDebug and Performance
Avalon-ST Bytes to Packets ConverterStreaming
Avalon-ST Channel AdapterStreaming
Avalon-ST JTAG InterfaceSerial
Avalon-ST Packets to Bytes ConverterStreaming
Avalon Packets to Transaction ConverterStreaming
On-Chip Memory (RAM or ROM)On Chip Memory
FamilyMAX 10
Altera MAX10 10M50 Rev C Development Kit Linux Setup (ACDS version 15.1)This page provides information about setting up and running Nios II Linux on Altera MAX10 10M50 Rev C development kit.
Development KitMAX 10 FPGA Development Kit
Quartus II VersionDownload Quartus II v16.0
Quartus II EditionStandard

Last updated on April 11, 2017, 11:52 a.m.