|Name||MAX 10 Single-Port Triple Speed Ethernet and On-Board PHY Chip Design Example|
|Description||This design example demonstrates Triple Speed Ethernet IP solution for MAX 10® device family using Altera® Triple Speed Ethernet MAC and Marvell 88E1111 PHY chip on MAX 10 FPGA Development Kit. It provides flexible test and demonstration platforms on which you can control, test, and monitor the Ethernet operations using system loopbacks. In this design, the Single-Port Triple-Speed Ethernet MAC connects to the on-board PHY chip through the Reduce Gigabit Media Independent Interface (RGMII).|
|Development Kit||MAX 10 FPGA Development Kit|
Note: After downloading the design example, you must prepare the design template. The file you downloaded is of the form of a <project>.par file which contains a compressed version of your design files (similar to a .qar file) and metadata describing the project. The combination of this information is what constitutes a <project>.par file. In releases 16.0 or newer, you can simply double click on the <project>.par file and Quartus will launch that project.
Browse to the <project>.par file you downloaded, click next, followed by Finish, and your design template will be installed and displayed in the Project Navigator pane in Quartus.
Note: When a design is stored in the Design Store as a design template, it has been previously regression tested against the stated version of Quartus software. The regression ensures the design template passes analysis/synthesis/fitting/assembly steps in the Quartus design flow.
At the command-line, type the following command:
Once the process completes, then type:
|Total Downloads||176 (From 09 Jun 2016 to 04 Oct 2017)|
|Quartus II Version||Download Quartus II v16.0|
|Quartus II Edition||Standard|
Last updated on June 9, 2016, 3:13 p.m.