Design Store

GPIO, QSPI Flash, UART, ADC, LEDs, Switches Design Example  

CategoryDesign Example
NameGPIO, QSPI Flash, UART, ADC, LEDs, Switches Design Example
DescriptionThis design example is used to check out general purpose interfaces on MAX 10 FPGA development kit, such as LEDs, DIPSW, PB, USB side-bus, PMOD, QSPI Flash, DAC, UART as well as GPIO-attribute ADC interface. Please download the installer of MAX 10 FPGA development kit and use BTS GUI to try it out.
Operating SystemNone
IP Core
IP CoreHeading
PIO (Parallel I/O)Peripherals
Altera Dual BootConfiguration
Altera Generic QUAD SPI controllerFlash
Altera ASMI ParallelConfiguration and Programming
Altera EPCQ Serial Flash controller coreOther
Altera SOFT ASMIBLOCKConfiguration and Programming
Avalon-ST Bytes to Packets ConverterStreaming
Avalon-ST Channel AdapterStreaming
Avalon-ST Single Clock FIFOOn Chip Memory
Avalon-ST JTAG InterfaceSerial
Avalon-ST Packets to Bytes ConverterStreaming
Reset ControllerClocks; PLLs and Resets
Avalon-ST Timing AdapterStreaming
Avalon Packets to Transaction ConverterStreaming
MM InterconnectMerlin Components
Avalon-MM Slave AgentMemory-Mapped
Avalon-MM Slave TranslatorMemory-Mapped
Avalon-ST AdapterStreaming
Avalon-ST Error AdapterStreaming
Memory-Mapped DemultiplexerMemory-Mapped
Memory-Mapped MultiplexerMemory-Mapped
Avalon-ST Handshake Clock CrosserStreaming
Avalon-MM Master AgentMemory-Mapped
Memory-Mapped Traffic LimiterMemory-Mapped
Avalon-MM Master TranslatorMemory-Mapped
Memory-Mapped RouterMemory-Mapped
UART (RS-232 Serial Port)Serial
USB Debug MasterDebug and Performance
USB Debug FIFOsDebug & Performance
FamilyMAX 10
Rev C installerGet the Rev C installer for this page. This has the BoardTestSystem application required to test the design.
GPIOs Flash Uart Interfaces Using the MAX 10 FPGA Development KitThis is a simple design spec for general purpose user I/O components example design for MAX 10 FPGA development kit. Note: Make sure the DIP switches on the back of the board are the default settings as shown in the user guide.
Development KitMAX 10 FPGA Development Kit
Installation Package

Note: After downloading the design example, you must prepare the design template. The file you downloaded is of the form of a <project>.par file which contains a compressed version of your design files (similar to a .qar file) and metadata describing the project. The combination of this information is what constitutes a <project>.par file. In releases 16.0 or newer, you can simply double click on the <project>.par file and Quartus will launch that project.

The second means to bring up the project template is through the New Project Wizard (File -> New Project Wizard). After entering the project name and folder on the first panel, the second panel will ask you to specify an empty project or project template. Select project template. You will see a list of Design Templates projects that you have loaded prior as well as various "Baseline Pinout Designs" that contain the pinout and settings for a variety of development kits. If you don't see your design template in the list, click on the link that states install the Design Templates circled below:

Browse to the <project>.par file you downloaded, click next, followed by Finish, and your design template will be installed and displayed in the Project Navigator pane in Quartus.

Note: When a design is stored in the Design Store as a design template, it has been previously regression tested against the stated version of Quartus software. The regression ensures the design template passes analysis/synthesis/fitting/assembly steps in the Quartus design flow.

At the command-line, type the following command:

quartus_sh --platform_install –package <project directory>/bts_config.par

Once the process completes, then type:

quartus_sh --platform –name bts_config

Total Downloads308 (From 17 May 2016 to 04 Oct 2017)
Quartus II VersionDownload Quartus II v16.0
Quartus II EditionStandard

Last updated on May 17, 2016, 2:23 p.m.