Design Store

FPGA Intro Example with PLL, Mux and Counter  

CategoryTutorial
NameFPGA Intro Example with PLL, Mux and Counter
DescriptionThis design example will guide the student through the complete design cycle from Design Entry to Configuring the MAX 10 on the MAX 10 FPGA Development Kit. This is the final solution of this lab. Refer to the documentation on how to recreate this design example.
Operating SystemNone
IP Core
IP CoreHeading
Avalon ALTPLLPLL
LPM_COUNTERArithmetic
Version1.0
FamilyMAX 10
Device10M50DA
Documentation
DocumentDescription
FPGA Intro Lab Manual (for Arrow DECA kit)-
Release Notes for Running FPGA Intro Lab on the MAX 10 Development Kit-
Development KitMAX 10 FPGA Development Kit
Installation Package Download

Note: After downloading the design example, you must prepare the design template. The file you downloaded is of the form of a <project>.par file which contains a compressed version of your design files (similar to a .qar file) and metadata describing the project. The combination of this information is what constitutes a <project>.par file. In releases 16.0 or newer, you can simply double click on the <project>.par file and Quartus will launch that project.

The second means to bring up the project template is through the New Project Wizard (File -> New Project Wizard). After entering the project name and folder on the first panel, the second panel will ask you to specify an empty project or project template. Select project template. You will see a list of Design Templates projects that you have loaded prior as well as various "Baseline Pinout Designs" that contain the pinout and settings for a variety of development kits. If you don't see your design template in the list, click on the link that states install the Design Templates circled below:


Browse to the <project>.par file you downloaded, click next, followed by Finish, and your design template will be installed and displayed in the Project Navigator pane in Quartus.

Note: When a design is stored in the Design Store as a design template, it has been previously regression tested against the stated version of Quartus software. The regression ensures the design template passes analysis/synthesis/fitting/assembly steps in the Quartus design flow.

At the command-line, type the following command:

quartus_sh --platform_install –package <project directory>/FPGA_Intro.par

Once the process completes, then type:

quartus_sh --platform –name FPGA_Intro

Total Downloads81 (From 17 May 2016 to 21 Jun 2017)
Quartus II Version Download Quartus II v16.0
Quartus II EditionStandard
VendorAltera


Image 2


Last updated on Oct. 19, 2016, 9:02 p.m.