Design Store

Drive on Chip Multi Axis Motor Control (FalconEye) (AN773)  

CategoryDesign Example
NameDrive on Chip Multi Axis Motor Control (FalconEye) (AN773)
DescriptionDrive on chip reference design for MAX10 development kit and DevBoards FalconEye 2 HSMC power board. Note that this design uses DDR3 memory and the pinout on the devkit changes based on the revision of your kit. See the MAX 10 dev kit baseline pinout design for a TCL script with the pinout changes between the different revisions of the development kits. The default setup requires a Rev C dev kit.
Operating SystemOther
IP Core
IP CoreHeading
Avalon-MM Pipeline BridgeMemory Mapped
Avalon-MM Clock Crossing BridgeMemory Mapped
Nios II Gen2 ProcessorNios
Custom Instruction Slave TranslatorNios II Custom Instructions
Custom Instruction InterconnectNios II Custom Instructions
Custom Instruction Master TranslatorNios II Custom Instructions
Interval TimerPeripherals
PIO (Parallel I/O)Peripherals
SPI (3 Wire Serial)Serial
MM InterconnectMerlin Components
Avalon-ST AdapterStreaming
Avalon-ST Error AdapterStreaming
Memory-Mapped DemultiplexerMemory-Mapped
Memory-Mapped MultiplexerMemory-Mapped
Avalon-ST Handshake Clock CrosserStreaming
Avalon-MM Slave AgentMemory-Mapped
Avalon-ST Single Clock FIFOOn Chip Memory
Avalon-MM Slave TranslatorMemory-Mapped
Avalon-MM Master AgentMemory-Mapped
Memory-Mapped Traffic LimiterMemory-Mapped
Avalon-MM Master TranslatorMemory-Mapped
Memory-Mapped RouterMemory-Mapped
Reset ControllerClocks; PLLs and Resets
Altera Generic QUAD SPI controllerFlash
Altera ASMI ParallelConfiguration and Programming
Altera EPCQ Serial Flash controller coreOther
Altera SOFT ASMIBLOCKConfiguration and Programming
IRQ MapperInterrupt
IRQ Clock CrosserInterrupt
altera_jtag_avalon_masterSystem
Avalon-ST Bytes to Packets ConverterStreaming
Avalon-ST Channel AdapterStreaming
Avalon-ST JTAG InterfaceSerial
Avalon-ST Packets to Bytes ConverterStreaming
Avalon-ST Timing AdapterStreaming
Avalon Packets to Transaction ConverterStreaming
DDR3 SDRAM Controller with UniPHYMemory Interfaces with UniPHY
Altera DDR3 Nextgen Memory ControllerMemory Controllers
Altera Nextgen Memory Controller MM-ST AdapterMemory Controller Components
Altera DDR3 Nextgen Memory Controller CoreMemory Controller Components
Altera DDR3 AFI MultiplexerMemory AFI Multiplexers
DDR3 SDRAM External Memory PHYMemory PHYs
DDR3 SDRAM External Memory PLL/DLL/OCT blockMemory PHYs
DDR3 SDRAM Qsys SequencerMemory Sequencers
Memory-Mapped Burst AdapterMemory-Mapped
Memory-Mapped Width AdapterMemory-Mapped
Floating Point Hardware 2Nios II Custom Instructions
Floating Point Hardware 2 CombinatorialFloating Point
Floating Point Hardware 2 Multi-cycleFloating Point
Performance Counter UnitDebug and Performance
Avalon ALTPLLPLL
On-Chip Memory (RAM or ROM)On Chip Memory
System ID PeripheralDebug and Performance
Version1.0
FamilyMAX 10
Device10M50DA
Documentation
DocumentDescription
Drive-On-Chip Reference Design v16.0 AN 773Application Note
Development KitMAX 10 FPGA Development Kit
Installation Package

Note: After downloading the design example, you must prepare the design template. The file you downloaded is of the form of a <project>.par file which contains a compressed version of your design files (similar to a .qar file) and metadata describing the project. The combination of this information is what constitutes a <project>.par file. In releases 16.0 or newer, you can simply double click on the <project>.par file and Quartus will launch that project.

The second means to bring up the project template is through the New Project Wizard (File -> New Project Wizard). After entering the project name and folder on the first panel, the second panel will ask you to specify an empty project or project template. Select project template. You will see a list of Design Templates projects that you have loaded prior as well as various "Baseline Pinout Designs" that contain the pinout and settings for a variety of development kits. If you don't see your design template in the list, click on the link that states install the Design Templates circled below:


Browse to the <project>.par file you downloaded, click next, followed by Finish, and your design template will be installed and displayed in the Project Navigator pane in Quartus.

Note: When a design is stored in the Design Store as a design template, it has been previously regression tested against the stated version of Quartus software. The regression ensures the design template passes analysis/synthesis/fitting/assembly steps in the Quartus design flow.

At the command-line, type the following command:

quartus_sh --platform_install –package <project directory>/DOC_FE2H_MAX10.par

Once the process completes, then type:

quartus_sh --platform –name DOC_FE2H_MAX10

Download
Total Downloads52 (From 26 Jan 2017 to 04 Oct 2017)
Quartus II VersionDownload Quartus II v16.0
Quartus II EditionStandard
VendorAltera


Last updated on Jan. 26, 2017, 11:24 a.m.