Design Store

Board Update Portal: Nios II, Flash,DDR3, Triple-Speed Ethernet, UART  

CategoryDesign Example
NameBoard Update Portal: Nios II, Flash,DDR3, Triple-Speed Ethernet, UART
DescriptionThis example design is a web-server based board update portal (BUP) design which contains a Nios® II processor, a Triple Speed Ethernet media access control (MAC) MegaCore® and a DDR3 MegaCore®. It allows you to remotely update a FPGA system over Ethernet, for an example, it can be used to update the firmware of an embedded FPGA system. The design is based on Ethernet A port on MAX 10 FPGA development kit, please download and install the BTS installer for more details about BUP design. Also, please see application note AN429: Remote Configuration Over Ethernet with the Nios® II Processor (PDF) to learn more about remote update. Note that this design uses DDR3 memory and the pinout on the devkit changes based on the revision of your kit. See the MAX 10 dev kit baseline pinout design for a TCL script with the pinout changes between the different revisions of the development kits.
Operating SystemNone
IP Core
IP CoreHeading
ALTCLKCTRLClocks; PLLs and Resets
Altera GPIO LiteIO
Avalon-ST AdapterStreaming
Avalon-ST Timing AdapterStreaming
Nios II Gen2 ProcessorNios
On-Chip Memory (RAM or ROM)On Chip Memory
Altera Dual BootConfiguration
Triple-Speed EthernetEthernet
Altera Generic QUAD SPI controllerFlash
Altera ASMI ParallelConfiguration and Programming
Altera EPCQ Serial Flash controller coreOther
Altera SOFT ASMIBLOCKConfiguration and Programming
IRQ MapperInterrupt
IRQ Clock CrosserInterrupt
PIO (Parallel I/O)Peripherals
DDR3 SDRAM Controller with UniPHYMemory Interfaces with UniPHY
Altera DDR3 Nextgen Memory ControllerMemory Controllers
Altera Nextgen Memory Controller MM-ST AdapterMemory Controller Components
Altera DDR3 Nextgen Memory Controller CoreMemory Controller Components
Altera DDR3 AFI MultiplexerMemory AFI Multiplexers
DDR3 SDRAM External Memory PHYMemory PHYs
DDR3 SDRAM External Memory PLL/DLL/OCT blockMemory PHYs
DDR3 SDRAM Qsys SequencerMemory Sequencers
Avalon-MM Master AgentMemory-Mapped
Avalon-MM Master TranslatorMemory-Mapped
Avalon-MM Slave AgentMemory-Mapped
Avalon-ST Single Clock FIFOOn Chip Memory
Avalon-MM Slave TranslatorMemory-Mapped
MM InterconnectMerlin Components
Avalon-ST Error AdapterStreaming
Memory-Mapped DemultiplexerMemory-Mapped
Memory-Mapped MultiplexerMemory-Mapped
Memory-Mapped Traffic LimiterMemory-Mapped
Avalon-ST Handshake Clock CrosserStreaming
Memory-Mapped Burst AdapterMemory-Mapped
Memory-Mapped RouterMemory-Mapped
Reset ControllerClocks; PLLs and Resets
Scatter-Gather DMA ControllerDMA
Interval TimerPeripherals
System ID PeripheralDebug and Performance
FamilyMAX 10
Board_Update_Portal_based_on_NIOS_II_Processor_Using_MAX_10_FPGA_Development_KitThis is a simple design spec of BUP design example for MAX 10 FPGA development kit
Development KitMAX 10 FPGA Development Kit
Installation Package

Note: After downloading the design example, you must prepare the design template. The file you downloaded is of the form of a <project>.par file which contains a compressed version of your design files (similar to a .qar file) and metadata describing the project. The combination of this information is what constitutes a <project>.par file. In releases 16.0 or newer, you can simply double click on the <project>.par file and Quartus will launch that project.

The second means to bring up the project template is through the New Project Wizard (File -> New Project Wizard). After entering the project name and folder on the first panel, the second panel will ask you to specify an empty project or project template. Select project template. You will see a list of Design Templates projects that you have loaded prior as well as various "Baseline Pinout Designs" that contain the pinout and settings for a variety of development kits. If you don't see your design template in the list, click on the link that states install the Design Templates circled below:

Browse to the <project>.par file you downloaded, click next, followed by Finish, and your design template will be installed and displayed in the Project Navigator pane in Quartus.

Note: When a design is stored in the Design Store as a design template, it has been previously regression tested against the stated version of Quartus software. The regression ensures the design template passes analysis/synthesis/fitting/assembly steps in the Quartus design flow.

At the command-line, type the following command:

quartus_sh --platform_install –package <project directory>/m10_rgmii.par

Once the process completes, then type:

quartus_sh --platform –name m10_rgmii

Total Downloads214 (From 18 Jul 2016 to 04 Oct 2017)
Quartus II VersionDownload Quartus II v16.0
Quartus II EditionStandard

Last updated on July 18, 2016, 11:47 a.m.