Design Store

ADC Data Capture with Nios II Processor  

CategoryDesign Example
NameADC Data Capture with Nios II Processor
DescriptionIn this design example you will implement the MAX 10 ADC hard IP. You will replace the simple hardware driver with a Nios II processor system.
Note that this is a design extracted from Arrow's DECA workshop series of labs. This is the final solution only. If you would like to work through the lab and learn more about it, visit: http://www.arrow.com/campaigns-na/altera/deca/.
Operating SystemNone
IP Core
IP CoreHeading
JTAG Debug Link (internal module)ConfigurationProgramming
Avalon-ST Bytes to Packets ConverterQsysInterconnect
Avalon-ST Single Clock FIFOQsysInterconnect
Avalon-ST Timing AdapterQsysInterconnect
Avalon-ST JTAG InterfaceQsysInterconnect
Avalon-ST Packets to Bytes ConverterQsysInterconnect
Avalon ST Debug FabricQsysInterconnect
Avalon-ST DemultiplexerQsysInterconnect
Avalon-ST Dual Clock FIFOQsysInterconnect
Avalon-ST Channel AdapterQsysInterconnect
Altera Management Reset BlockDebug and Performance
Reset ControllerQsysInterconnect
Avalon-ST MultiplexerQsysInterconnect
Trace FabricQsysInterconnect
Avalon-ST AdapterQsysInterconnect
Avalon-ST Data Format AdapterQsysInterconnect
Avalon-MM Pipeline BridgeQsysInterconnect
altera_trace_capture_controllerQsysInterconnect
Avalon-ST Pipeline StageQsysInterconnect
On-Chip Memory (RAM or ROM)OnChipMemory
MM InterconnectQsysInterconnect
Avalon-ST Error AdapterQsysInterconnect
Avalon-MM Slave AgentQsysInterconnect
Avalon-MM Slave TranslatorQsysInterconnect
Memory-Mapped DemultiplexerQsysInterconnect
Memory-Mapped MultiplexerQsysInterconnect
Memory-Mapped RouterQsysInterconnect
Avalon-MM Master AgentQsysInterconnect
Memory-Mapped Traffic LimiterQsysInterconnect
Avalon-MM Master TranslatorQsysInterconnect
Trace ROMQsysInterconnect
Timestamp monitorQsysInterconnect
transacto_liteSimulationDebugVerification
Altera Modular ADC coreADC
Altera Trace ADC MonitorADC
Altera Trace ADC Monitor CoreADC
Altera Trace ADC Monitor Width AdapterADC
altera_trace_monitor_endpointQsysInterconnect
Altera Modular ADC Control coreADC
Altera Modular ADC Sample Storage coreADC
Altera Modular ADC Sequencer coreADC
Avalon-ST SplitterQsysInterconnect
IRQ MapperQsysInterconnect
IRQ Clock CrosserQsysInterconnect
PIO (Parallel I/O)Peripherals
Avalon-ST Handshake Clock CrosserQsysInterconnect
JTAG UARTConfigurationProgramming
Nios II Gen2 ProcessorNiosII
Nios II Gen2 Processor UnitNiosII
IRQ BridgeQsysInterconnect
System ID PeripheralDebug and Performance
Interval TimerPeripherals
Avalon ALTPLLClocksPLLsResets
Version1.0
FamilyMAX 10
Device10M50DA
Documentation
DocumentDescription
ADC Data Capture Lab Manual-
Arrow DECA Product Page-
Development KitArrow MAX 10 DECA
Installation Package

Note: After downloading the design example, you must prepare the design template. The file you downloaded is of the form of a <project>.par file which contains a compressed version of your design files (similar to a .qar file) and metadata describing the project. The combination of this information is what constitutes a <project>.par file. In releases 16.0 or newer, you can simply double click on the <project>.par file and Quartus will launch that project.

The second means to bring up the project template is through the New Project Wizard (File -> New Project Wizard). After entering the project name and folder on the first panel, the second panel will ask you to specify an empty project or project template. Select project template. You will see a list of Design Templates projects that you have loaded prior as well as various "Baseline Pinout Designs" that contain the pinout and settings for a variety of development kits. If you don't see your design template in the list, click on the link that states install the Design Templates circled below:


Browse to the <project>.par file you downloaded, click next, followed by Finish, and your design template will be installed and displayed in the Project Navigator pane in Quartus.

Note: When a design is stored in the Design Store as a design template, it has been previously regression tested against the stated version of Quartus software. The regression ensures the design template passes analysis/synthesis/fitting/assembly steps in the Quartus design flow.

At the command-line, type the following command:

quartus_sh --platform_install –package <project directory>/ADC_Nios_Lab.par

Once the process completes, then type:

quartus_sh --platform –name ADC_Nios_Lab

Download
Total Downloads164 (From 13 Jun 2016 to 17 Nov 2017)
Quartus II VersionDownload Quartus II v16.0
Quartus II EditionStandard
VendorArrow


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Last updated on Oct. 17, 2016, 5:51 p.m.