Design Store

ADC Data Capture with Hardware Streaming using ADC Toolkit Display  

CategoryDesign Example
NameADC Data Capture with Hardware Streaming using ADC Toolkit Display
DescriptionIn this design example you will implement the MAX 10 ADC hard IP using hardware-only streaming.
Note that this is a design extracted from Arrow's DECA workshop series of labs.This is the final solution only. If you would like to work through the lab and learn more about it, visit:
Operating SystemNone
IP Core
IP CoreHeading
JTAG Debug Link (internal module)Debug and Performance
Avalon-ST Bytes to Packets ConverterStreaming
Avalon-ST Single Clock FIFOOn Chip Memory
Avalon-ST Timing AdapterStreaming
Avalon-ST JTAG InterfaceSerial
Avalon-ST Packets to Bytes ConverterStreaming
Avalon ST Debug FabricDebug & Performance
Avalon-ST DemultiplexerStreaming
Avalon-ST Dual Clock FIFOOn Chip Memory
Avalon-ST Channel AdapterStreaming
Altera Management Reset BlockDebug and Performance
Reset ControllerClocks; PLLs and Resets
Avalon-ST MultiplexerStreaming
Trace FabricDebug & Performance
Avalon-ST AdapterStreaming
Avalon-ST Data Format AdapterStreaming
Avalon-MM Pipeline BridgeMemory Mapped
Avalon-ST Pipeline StageStreaming
On-Chip Memory (RAM or ROM)On Chip Memory
MM InterconnectMerlin Components
Avalon-ST Error AdapterStreaming
Avalon-MM Slave AgentMemory-Mapped
Avalon-MM Slave TranslatorMemory-Mapped
Memory-Mapped DemultiplexerMemory-Mapped
Memory-Mapped MultiplexerMemory-Mapped
Memory-Mapped RouterMemory-Mapped
Avalon-MM Master AgentMemory-Mapped
Memory-Mapped Traffic LimiterMemory-Mapped
Avalon-MM Master TranslatorMemory-Mapped
Trace ROMTrace
Timestamp monitorTrace
Altera Modular ADC corePeripherals
Altera Trace ADC MonitorOther
Altera Trace ADC Monitor CoreOther
Altera Trace ADC Monitor Width AdapterOther
altera_trace_monitor_endpointDebug & Performance
Altera Modular ADC Control corePeripherals
Altera Modular ADC Sequencer corePeripherals
Avalon-ST SplitterStreaming
FamilyMAX 10
ADC Data Capture Lab Manual-
Arrow DECA Product Page-
Development KitArrow MAX 10 DECA
Installation Package

Note: After downloading the design example, you must prepare the design template. The file you downloaded is of the form of a <project>.par file which contains a compressed version of your design files (similar to a .qar file) and metadata describing the project. The combination of this information is what constitutes a <project>.par file. In releases 16.0 or newer, you can simply double click on the <project>.par file and Quartus will launch that project.

The second means to bring up the project template is through the New Project Wizard (File -> New Project Wizard). After entering the project name and folder on the first panel, the second panel will ask you to specify an empty project or project template. Select project template. You will see a list of Design Templates projects that you have loaded prior as well as various "Baseline Pinout Designs" that contain the pinout and settings for a variety of development kits. If you don't see your design template in the list, click on the link that states install the Design Templates circled below:

Browse to the <project>.par file you downloaded, click next, followed by Finish, and your design template will be installed and displayed in the Project Navigator pane in Quartus.

Note: When a design is stored in the Design Store as a design template, it has been previously regression tested against the stated version of Quartus software. The regression ensures the design template passes analysis/synthesis/fitting/assembly steps in the Quartus design flow.

At the command-line, type the following command:

quartus_sh --platform_install –package <project directory>/ADC_Streaming_Lab.par

Once the process completes, then type:

quartus_sh --platform –name ADC_Streaming_Lab

Total Downloads145 (From 13 Jun 2016 to 17 Nov 2017)
Quartus II VersionDownload Quartus II v16.0
Quartus II EditionStandard

Image 3

Last updated on Oct. 5, 2016, 10:41 a.m.