Design Store

DECA Graphics Design Example  

CategoryDesign Example
NameDECA Graphics Design Example
DescriptionThis design implements frame buffer based graphics on Altera MAX10 Arrow/Terasic DECA board in VIP (Video and Image Processing Suite).
Operating SystemLinux
IP Core
IP CoreHeading
Frame ReaderVideo and Image Processing
PIO (Parallel I/O)Peripherals
Clocked Video Output II (4K Ready)Video and Image Processing
CVO schedulerComponent Library
IRQ MapperInterrupt
IRQ Clock CrosserInterrupt
DDR3 SDRAM Controller with UniPHYMemory Interfaces with UniPHY
Altera DDR3 Nextgen Memory ControllerMemory Controllers
Altera Nextgen Memory Controller MM-ST AdapterMemory Controller Components
Altera DDR3 Nextgen Memory Controller CoreMemory Controller Components
Altera DDR3 AFI MultiplexerMemory AFI Multiplexers
DDR3 SDRAM External Memory PHYMemory PHYs
DDR3 SDRAM External Memory PLL/DLL/OCT blockMemory PHYs
DDR3 SDRAM Qsys SequencerMemory Sequencers
Avalon-MM Master AgentMemory-Mapped
Avalon-MM Master TranslatorMemory-Mapped
Avalon-MM Slave AgentMemory-Mapped
Avalon-ST Single Clock FIFOOn Chip Memory
Avalon-MM Slave TranslatorMemory-Mapped
MM InterconnectMerlin Components
Memory-Mapped Width AdapterMemory-Mapped
Avalon-ST AdapterStreaming
Avalon-ST Error AdapterStreaming
Memory-Mapped DemultiplexerMemory-Mapped
Memory-Mapped MultiplexerMemory-Mapped
Avalon-ST Handshake Clock CrosserStreaming
Memory-Mapped Burst AdapterMemory-Mapped
Memory-Mapped Traffic LimiterMemory-Mapped
Memory-Mapped RouterMemory-Mapped
Nios II Gen2 ProcessorNios
On-Chip Memory (RAM or ROM)On Chip Memory
Reset ControllerClocks; PLLs and Resets
System ID PeripheralDebug and Performance
Interval TimerPeripherals
Test Pattern Generator II (4K Ready)Video and Image Processing
Mixer II (4K Ready)Video and Image Processing
alt_vip_cvo_coreComponent Library
FamilyMAX 10
Link to
Development KitArrow MAX 10 DECA
Quartus II VersionDownload Quartus II v15.0
Quartus II EditionStandard

Last updated on Nov. 6, 2016, 10:11 p.m.